Spade, a hardware description language inspired by modern software languages
53 points by kaycebasques
53 points by kaycebasques
đź‘‹ Spade author here, fun to see my little language get spread around!
Got a Cologne Chip Gate Mate a while back and started tinkering with it. 30 minutes in, I had my first blinky LED binary counter up and running. Another 40 minutes later I had the same, but implemented in Spade, up and running. Mind you, this is not an endorsement of my FPGA skillz, I hadn’t touched VHDL/Verilog in half a decade at that point.
Compare that to the 2.5h hours it takes to install a recent AMD Xilinx Vivado on a fast computer, it is astonishing to me how good the developer UX in the Open Source FPGA world got. I hope Spade will become industry relevant some time soon (that is, soon in this context means in the next decade, I guess)!
Yeah, the commercial tools are incredibly sluggish :D
It would have been even better if we had gate mate support in swim, then just swim install tools, swim init --board gatemate and swim upload would have been enough :)
I’m deeply perplexed by how this is supposed to work. Is it supposed to be a more or less direct “contender” to the same niche that VHDL/Verilog fills, or..?
Yep, that’s the idea VHDL and Verilog to me feel very antiquated so I wanted to build something more modern.
We also try to raise the abstraction level a little bit with pipelines in the language, ready valid interfaces being modelled in the type system etc. though without sacrificing low level performance. Broadly like moving from C to Rust or C++
On a technical level, Spade is a transpiler IIUC, so Spade lang compiles to Verilog. So all the vendor tooling for synthesis and place’n route still can be used. A bit like Typescript and JavaScript, if you will.
Yeah, that’s a good point, for compiling to any hardware, emitting Verilog or VHDL is pretty much the only option at the moment since that’s the lowest level that you can reliably feed to tools. I also wouldn’t want to emit anything much lower level since that’d soon devolve into having to do synthesis
Offtopic, but a fellow HDL developer has a pretty good case against the use of “transpiler” https://rachit.pl/post/transpiler/, even if in this case it is quite clear what the distinction is
It is more of a Spinal/Chisel/Bluespec competitor, folks using Verilog are the least likely to use this.
This looks neat. I like the pipeline structure. I’d love to see an example of a superscalar design, with different-length pipelines. It wasn’t really clear to me how backpressure works in this kind of design from skimming the book. I can see lower-level features for building these things but they seem to be quite different from the high-level abstractions and I’d worry that I’d hit a cliff and have to completely rewrite some things.