Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance

This is a fascinating article and I'm glad I read it, but I think the title is clickbait. I think that the superscalar design they're comparing against doesn't have the ALU muscle that a superscalar needs to really benefit from being a superscalar (as opposed to using dual-issue as a low-effort-high-return way to overcome pipeline restrictions). It's true that they got very close to the performance of a superscalar design, but I think describing it in terms of "superscalar performance" is misleading.

https://mummanajagadeesh.github.io/projects/rose/rv32im/#rv32i-superscalar-2-way-in-order

Lower hardware cost than single-cycle (shared ALU, smaller muxes)

....But this line is also on the page for their single-cycle design, so....???