Everyone Says Assembly Is Untyped—Everyone Is Wrong

“Why even bother having its own inline assembler” — I really feel that people who say things like this have never actually used a compiler with integrated assembly. It is so much more pleasant, easier to manage, and easier to reason about than the asm string model we get in clang and gcc.

I really do wish more people would see what other languages/compilers do for features they dismiss before dismissing them.

destination-first is not an Intel quirk, it is the majority convention across ISAs. ARM writes add r0, r1, r2 (destination first)

Well, except for load and store instructions: an LDM puts the source address on the left and the destination registers on the right; an STR or STP puts the source registers on the left and the destination address on the right. The inconsistency is because ARM asm roughly matches the instruction layout, reading left to right most significant end to least significant end. The LDR and STR instructions put their address operands in the same place, so source and destination are in the opposite order for load and store; but LDM and STM put their address operands in a different field so they read the opposite way round to LDR and STR.

Weirdly I don’t remember really noticing this inconsistency when I was learning arm asm!

Pretty cool - especially extracting out the flag registers (that always has per-language specific inline-asm syntax which is very unintuitive).

The premise of the article makes sense at the instruction granularity, and the input from Odin into the instruction stream, but it doesnt touch on whether there's typechecking across asm instructions (i.e. paddps xmm0, xmm1; paddpd xmm0, xmm1). There's valid cases where a register can "change" its type for the next instruction. At the PL level, thats explicitly done with a typecast. But in asm, its sorta implicit. It's one of the last places where you could say that registers/memory are untyped.

I noticed from the article that Odin has an assembler as library, and that it may have a 6502 target. I would have loved to see an example of inline assembly with that CPU, as it's a difficult target for a compiler (only three 8-bit registers, none of which are general purpose).