This PCB is brought to you by Fable 5

This comment stood out to me:

The feedback would be about routing practices and component placement. For example, the low hanging fruit as it were, there are reference designs directly from the raspberry pi foundation for this chip, freely available. Given the ample amount of room, there is no reason not to copy that layout wholesale onto this board, allowing differences only for the new components. I'm not saying you're not allowed to be a bit creative, but if the goal is to make something that definitely works, and you have full access to a design that definitely works, at scale, then you should use that unless you can make a very clear argument not to. People may change it up if they're trying to do something that the original design doesn't allow for, maybe they want to minimize board area or layer count for example, by there is none of that here.

This reminds me of the claude-generated Python HTML5 parser that was hyped on HN a few months ago. Sure, it's a lot of gruntwork, but unless you're aiming for performance it's not complex at all, there's so much reference material and reusable testsuites that it's very likely to succeed too.

DRC is an obvious step basically like running a software linter — which weirdly is still something I have to tell Claude to do.

However, he didn’t mention actually setting the DRC rules to match the JLCPCB requirements, which (if so) he got away with because the KiCad defaults are conservative. Also because JLCPCB checks DRC and will auto-reject the design.

Edit: This also is a very LLM-friendly design in that it’s just a bunch of digital routing and a little bit of analog signal conditioning straight off the datasheet. It would be interesting to see if Fable is any better than its predecessors at making analog designs.